View GS9015BCPJ_2834207.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

not recommended for new designs genlinx ? gs9015b serial digital reclocker data sheet revision date: july 2004 features device description the gs9015b is a monolithic ic designed to receive smpte 259m serial digital video signals. this device performs the function of data and clock recovery. it interfaces directly with the genlinx ? gs9000b or gs9000s decoder. while there are no plans to discontinue the gs9015b, gennum has developed a successor product with improved features and performance called the gs9035. the gs9035 is recommended for new designs. the vco centre frequencies are controlled by external resistors which can be selected by applying a two bit binary code to the standards select input pins. alternatively, the gs9015b can be used with the gs9010a to form an adjustment free reclocker system. the gs9015b is packaged in a 28 pin plcc operating from a single +5 or -5 volt supply. ? reclocking of smpte 259m signals operational to 400 mb/s adjustment free reclocker when used with the gs9000b or gs9000s decoder and gs9010a automatic tuning sub-system 28 pin plcc packaging pb-free and green applications 4? sc , 4:2:2 and 360 mb/s serial digital interfaces special note: r vco1 and r vco2 are functional over a reduced temperature range of t a =0c to 50c. r vco0 and r vco3 are functional over the full temperature range of t a =0c to 70c. this limitation does not affect operation with the gs9010a ats. functional block diagram document no. 32467 - 0 gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 web site: www.gennum.com e-mail: info@gennum.com part number package temperature pb-free and green GS9015BCPJ 28 pin plcc 0c to 70c no gs9015bctj 23 pin plcc tape 0c to 70c no gs90015bcpje3 28 pin plcc 0c to 70c yes ordering information serial data pll serial clock loop filter ss0 ss1 carrier detect data latch phase comparator carrier detect charge pump standard select vco 19 12 13 14 15 17 20 21 serial data serial clock 24 25 22 23 2 ?/ 2 10 digital in 5,6 gs9015b
2 of 13 not recommended for new designs 32467 - 0 absolute maximum ratings parameter value/units supply voltage 5.5 v input voltage range (any input) v cc +0.5 to v ee -0.5 v dc input current (any one input) 5 ma power dissipation 750 mw operating temperature range 0c t a 70c storage temperature range -65c t s 150c lead temperature (soldering, 10 seconds) 260c parameter symbol conditions min typ max units notes supply voltage v s operating range 4.75 5.0 5.25 v power consumption p d - 330 500 mw supply current (total) i s - 87 120 ma see figure11 serial data & - high v oh t a = 25c -1.025 - -0.88 v with respect to v cc clock output - low v ol t a = 25c -1.9 - -1.6 v logic inputs - high v ih min +2.0 - - v with respect to v ee - low v il max - - +0.8 v with respect to v ee carrier detect v cdl r l = 10 k ? to v cc 0.2 0.4 v output voltage v cdh 4.0 5.0 - v serial data bit rate br sdo t a = 25c 100 - 400 mb/s serial clock frequency ? slk t a = 25c 100 - 400 mhz see figure 9 output signal swing v o t a = 25c 700 800 900 mv p-p see figure10 serial data to serial clock t d see waveforms - -500 - ps data lags clock lock times t lock see note 1 - - 10 s jitter t j t a = 25c, 270 mb/s - 100 - ps p-p see figure12 direct digital input v ddi 200 - 2000 mvp-p differential drive levels (5, 6) v s = 5v, t a = 0c to 70c, r l = 100 ? to (v cc - 2v) unless otherwise shown. (1, 10, 20, 21) gs9015b reclocker dc electrical characteristics with respect to v cc with respect to v ee open collector - active high parameter symbol condition min typ max units no tes synchronization v s = 5v, t a = 0c to 70c, r l = 100 ? to (v cc - 2v) unless otherwise shown. gs9015b reclocker ac electrical characteristics notes: 1. switching between two sources of the same data rate. caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation
3 of 13 32467 - 0 not recommended for new designs the gs9015b reclocking receiver is a bipolar integrated circuit containing circuitry necessary to re-clock and regenerate the nrzi serial data stream. packaged in a 28 pin plcc, the receiver operates from a single five volt supply at data rates to 400 mb/s. typical power consumption is 330 mw. typical output jitter is 100 ps at 270 mb/s. serial digital signals are applied to digital inputs ddi and ddi (pins 5,6). t d serial data out (sd0) 50% serial clock out (sck) t d 50% phase locked loop the phase comparator itself compares the position of transitions in the incoming signal with the phase of the local oscillator (vco). the error-correcting output signals are fed to the charge pump in the form of short pulses. the charge pump converts these pulses into a ?charge packet? which is accurately proportional to the system phase error. the charge packet is then integrated by the second-order loop filter to produce a control voltage for the vco. during periods when there are no transitions in the signal, the loop filter voltage is required to hold precisely at its last value so that the vco does not drift significantly between corrections. commutating diodes in the charge pump keep the output leakage current extremely low, minimizing vco frequency drift. the vco is implemented using a current-controlled multivibrator, designed to deliver good stability, low phase noise and wide operating frequency capability. the frequency range is design-limited to 10% about the oscillator centre frequency. fig.1 waveforms vco centre frequency selection the centre frequency of the vco is set by one of four external current reference resistors (rvco0-rvco3) connected to pins 13,14,15 or 17. these are selected by two logic inputs ss0 and ss1 (pins 20, 21) through a 2:4 decoder according to the following truth table. ss1 ss0 resistor selected 0 0 rvco0 (13) 0 1 rvco1 (14) 1 0 rvco2 (15) 1 1 rvco3 (17) as an alternative, the gs9010a automatic tuning sub-system and the gs9000b or gs9000s decoder may be used in conjunction with the gs9015b to obtain adjustment free and automatic standard select operation (see figure17). with the vco operating at twice the clock frequency, a clock phase which is centred on the eye of the locked signal is used to latch the incoming data, thus maximising immunity to jitter-induced errors. the alternate phase is used to latch the output re-clocked data sdo and sdo (pins 25, 24). the true and inverse clock signals themselves are available from the sco and sco pins 23 and 22. gs9015b reclocking receiver - detailed device description
4 of 13 not recommended for new designs 32467 - 0 gs9015b pin descriptions pin no. symbol type description 1v ee1 power supply . most negative power supply connection. 2v ee1 power supply . most negative power supply connection. 3v ee1 power supply. most negative power supply connection. 4v ee1 power supply. most negative power supply connection. 5,6 ddi/ddi input direct data inputs (true and inverse). pseudo-ecl, differential serial data inputs. they may be directly driven from true ecl drivers when v ee = -5v and v cc = 0 v. 7v cc1 power supply . most positive power supply connection. (phase detector, carrier detect). 8, 9 v ee1 power supply . most negative power supply connection. 10 ?/2 en input ?/2 enable- ttl compatible input used to enable the divide by 2 function. 11 v ee3 power supply. most negative power supply connection. (vco, mux, standard select) 12 loop filt loop filter. node for connecting the loop filter components. 13 r vco0 input vco resistor 0. analog current input used to set the centre frequency of the vco when the two standard select bits (pins 20 and 21) are set low. a resistor is connected from this pin to v ee . 14 r vco1 input vco resistor 1. analog current input used to set the centre frequency of the vco when standard select bit 0 (pin 20) is set high and bit 1 (pin 21) is set low. a resistor is connected from this pin to v ee . 15 r vco2 input vco resistor 2. analog current input used to set the centre frequency of the vco when standard select bit 0 (pin 20) is set low and bit 1 (pin 21) is set high. a resistor is connected from this pin to v ee . 16 v ee3 power supply . most negative power supply connection. 17 r vco3 input vco resistor 3. analog current input used to set the centre frequency of the vco when the two standard select bits (pins 20 and 21) are set high. a resistor is connected from this pin to v ee . fig. 2 gs9015b pin connections sd0 sd0 sc0 sc0 ss1 ss0 cd ddi ddi v cc1 v ee1 v ee1 v ee1 v ee1 v ee1 v ee1 v ee1 v ee2 v cc3 gs9015b top view loop r vco0 r vco1 r vco2 v ee3 r vco3 v cc2 filt 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 28 27 26 ? /2 en v ee3
5 of 13 32467 - 0 not recommended for new designs pin no symbol type description 18 v cc2 power supply. most positive power supply connection. (vco, mux, standard select). 19 cd output carrier detect . open collector output which goes high when a signal is present at either the serial data inputs or the direct digital inputs. this output is used in conjunction with the gs9000b or gs9000s in the automatic standards select mode to disable the 2 bit standard select counter. this pin should see a low ac impedance (e.g. 1nf to ac gnd) 20,21 ss0, ss1 inputs standard select inputs. ttl inputs to the 2:4 multiplexer used to select one of four vco centre frequency setting resistors (r vco0 - r vco3 ). when both ss0 and ss1 are low, r vco0 is selected. when ss0 is high and ss1 is low, r vco1 is selected. when ss0 is low and ss1 is high, r vco2 is selected and when both ss0 and ss1 are high, r vco3 is selected. these pins should see a low ac impedance (e.g. 1nf to ac gnd) 22,23 sco/sco outputs serial clock outputs (inverse and true). pseudo-ecl differential outputs of the extracted serial clock. these outputs require a 390 ? pull-down resistors to v ee . 24,25 sdo/sdo outputs serial data outputs (inverse and true). pseudo-ecl differential outputs of the regenerated serial data. these outputs require a 390 ? pull-down resistors to v ee . 26 v cc3 power supply. most positive power supply connection. (ecl outputs). 27 v ee2 power supply. most negative power supply connection. (phase detector, carrier detect) 28 v ee1 power supply . most negative power supply connection. gs9015b pin descriptions cont. + - 2k 2k 1k 1k 1.6v ddi pin 5 pin 6 ddi v cc 1.2v + - 380a fig. 3 pins 1, 5 and 6 input / output circuits
6 of 13 not recommended for new designs 32467 - 0 v cc3 sdo or sco pin 25, 24 10k 200 sdo or sco pin 23, 22 v cc v cc v cc 200 800 10k 3k i vco 400 pin 15 pin 17 r vco 0 pin 13 pin 14 400 400 400 r vco 1 r vco 2 r vco 3 loop filter (1.8 - 2.7v) (1.9 - 2.4v) input / output circuits cont. fig. 4 pins 13, 14, 15 and 17 fig. 5 pins 25, 24, 23 and 22
7 of 13 32467 - 0 not recommended for new designs input / output circuits cont. pin 12 loop filter v cc v cc 1k v cc 2k 1.5k fig. 6 pin 12 10k v cc pin 19 cd fig. 7 pin 19 v cc pin 20 sso v cc 40 a 40 a pin 21 ss1 v cc pin 10 ?/2 en v cc v cc + - 18 a 55 a 480 a 1.6v fig. 8 pins 20, 21 and 10
8 of 13 not recommended for new designs 32467 - 0 typical performance curves 500 450 400 350 300 250 200 150 100 50 1 2 3 4 5 6 7 8 9 10 frequency setting resistance (k ? ) fig. 9 clock frequency 0 10 20 30 40 50 60 70 temperature (c) fig. 11 supply current v s = 4.75v v s = 5.25v 900 850 800 750 700 650 600 0 10 20 30 40 50 60 70 temperature (c) fig. 10 serial outputs ?/2 off ?/2 on v s = 5.00v v s = 5.25v v s = 4.75v (v s = 5v, t a = 25c unless otherwise shown) 105 100 95 90 85 80 75 70 65 v s = 5.00v frequency (mhz) serial outputs (mv) (p-p) current (ma)
9 of 13 32467 - 0 not recommended for new designs test setup figure 12 shows a typical circuit for the gs9015b using a +5 volt supply. figure 13 shows the gs9015b connections when using a -5 volt supply. the 0.1f decoupling capacitors must be placed as close as possible to the corresponding vcc pins. the layout of the loop filter and rvco components requires careful attention. this has been detailed in an application note entitled "optimizing circuit and layout design of the gs9005a/15a", document no. 521 - 32 - 00. the loop voltage can be conveniently measured across the 10 nf capacitor in the loop filter. tuning procedures are described in the temperature compensation section (page 11). the fixed value frequency setting resistors should be placed close to the corresponding pins on the gs9015b. the carrier detect is an open-collector active high output requiring a pull-up resistor of approximately 10 k ? . the ss0, ss1, and cd pins should see a low ac impedance. this is particularly important when driving the ss0, ss1 pins with external logic. the use of 1nf decoupling capacitors at these pins ensures this. fig. 12 gs9015btypical test circuit using +5v supply all resistors in ohms, all capacitors in microfarads unless otherwise stated. ecl data inputs 0.1 100 100 100 100 390 390 390 390 data data clock clock 25 24 23 22 21 20 19 5 6 7 8 9 10 11 4 3 2 1 28 27 26 12 13 14 15 16 17 18 910 5.6p 10n see figure 15 +5v 1 2 0.1 10k carrier detect output +5v +5v +5v +5v gs9015b sdo sdo sco sco ss1 ss0 cd vee1 vee1 vee1 vee1 vee1 vee2 vcc3 loop rvco0 rvco1 rvco2 vee3 rvco3 vcc2 star routed loop voltage test point 0.1 dd i dd i vcc1 vee1 vee1 ?/2 vee3
10 of 13 not recommended for new designs 32467 - 0 fig. 13 gs9015b typical test circuit using -5v supply all resistors in ohms, all capacitors in microfarads unless otherwise stated. vco frequency setting resistors there are two modes of vco operation available in the gs9015b depending on the state of the 2 block. the 2 block is enabled according to : 2 enable = ?/2 ss1. when the ?/2 enable (pin 10) is low, any of the four vco frequency setting resistors, rvco0 through rvco3, (pins 13, 14, 15 and 17) may be used for any data rate from100 mb/s to 400 mb/s. for example, for 143 mb/s data rate, the value of the total rvco resistance is approximately 6k8 and for 270 mb/s operation, the value is approximately 3k5. the 5k potentiometers will then tune the desired data rate near their mid-points. jitter performance at the lower data rates (143, 177 mb/s) is improved by operating the vco at twice the normal frequency. this is accomplished by enabling the divide by two block in the pll section of the gs9015b. when ?/2 (pin 10) is high, two of the rvco pins are assigned to data rates below 200 mb/s and two are assigned to data rates over 200 mb/s. the selection is dependent upon the level of standard select bit, ss1 (pin 21). when ss1 is low, rvco0 and r vco1 (pins 13 and 14) are used for the higher data rates. when ss1 is high, the vco frequency is now twice the bit rate and its frequency is set by rvco2 and rvco3 (pins 15 and 17). for 143 mb/s and 270 mb/s operation, (the vco is at 286 mhz and 270 mhz respectively) the total resistance required is approximately the same for both data rates. this also applies for 177 mb/s and 360 mb/s operation (the vco is tuned to 354 mhz and 360 mhz respectively). this means that one potentiometer may be used for each frequency pair with only a small variation of the fixed resistor value. this halves the number of adjustments required. ecl data inputs -5v -5v -5v 100 100 100 100 390 390 390 390 0.1 25 24 23 22 21 20 19 5 6 7 8 9 10 11 4 3 2 1 28 27 26 12 13 14 15 16 17 18 910 5.6p 10n -5v 1 2 0.1 10k data carrier detect output data clock clock gs9015b dd i dd i vcc1 vee1 vee1 ?/2 vee3 sdo sdo sco sco ss1 ss0 cd vee1 vee1 vee1 vee1 vee1 vee2 vcc3 loop rvco0 rvco1 rvco2 v ee3 rvco3 vcc2 star routed loop voltage see figure 15 -5v -5v -5v 0.1
11 of 13 32467 - 0 not recommended for new designs 5.6k v ee 1n914 1.3k 5k divide by 2 is off 4.3k v ee 1n914 1.3k 5k divide by 2 is on v ee 1n914 1k 1k divide by 2 is off divide by 2 is on v ee 1n914 1k 1k 0.1f 0.1f 0.1f 0.1f fig. 14 frequency setting resistor values & temperature compensation divide by 2 is off v ee 1k 0.1f 5k figure 14 shows the connections for the frequency setting resistors for the various data rates. the compensation shown for 360 mb/s and 177 mb/s with divide by 2 on, is useful to a maximum ambient temperature of 50c. if the divide by 2 function is not enabled by the ?/2 enable input, no compensation is needed for the 143 mb/s and 177 mb/s data rates. the resistor connections are shown in figure 15. in both cases , the 0.1f capacitor that bypasses the potentiometer should be star routed to vee3. temperature compensation loop bandwidth the loop bandwidth is dependant upon the internal pll gain constants along with the loop filter components connected to pin 12. in addition, the impedance seen by the rvco pin also influences the loop characteristics such that as the imped- ance drops, the loop gain increases. applications circuit figure 16 shows an application of the gs9015b in an adjustment free, multi-standard serial to parallel convertor. this circuit uses the gs9010a automatic tuning sub- system ic and a gs9000b or gs9000s decoder ic. the gs9010a ats eliminates the need to manually set or externally temperature compensate the receiver or reclocker vco. the gs9010a can also determine whether the incoming data stream is 4?sc ntsc,4?sc pal or component 4:2:2. the gs9010a includes a ramp generator/oscillator which repeatedly sweeps the reclocker vco frequency over a set range until the system is correctly locked. an automatic fine tuning (aft) loop maintains the reclocker vco control voltage at it's centre point through continuous, long term adjustments of the vco centre frequency. during normal operation, the gs9000b or gs9000s decoder provides continuous hsync pulses which disable the ramp/oscillator of the gs9010a. this maintains the correct reclocker vco frequency. when an interruption to the incoming data stream is detected by the reclocker, the carrier detect goes low and opens the aft loop in order to maintain the correct vco frequency for a period of at least 2 seconds. this allows the reclocker to rapidly relock when the signal is re-established. 143mb/s and 177 mb/s using any r vco pins fig. 15 non - temperature compensated resistor values for 143 mb/s and 177 mb/s temperature compensation procedure in order to correctly set the vco frequency so that the pll will always re-acquire lock over the full temperature range, the following procedure should be used. the circuit should be powered on for at least one minute prior to starting this procedure. monitor the loop filter voltage at the junction of the loop filter resistor and 10 nf loop filter capacitor (loop filter test point). using the appropriate network shown above, the vco frequency is set by first tuning the potentiometer so that the pll loses lock at the low end (lowest loop filter voltage). the loop filter voltage is then slowly increased by adjusting the the potentiometer to determine the error free low limit of the capture range. error free operation is determined by using a suitable crc or edh measurement method to obtain a stable signal with no errors. record the loop filter voltage at this point as v cl . now adjust the potentiometer so that the loop filter voltage is 250 mv above v cl . 270 mb/s using r vco0 or r vco1 143 mb/s using r vco2 or r vco3 177 mb/s using r vco2 or r vco3 360 mb/s using r vco0 or r vco1
12 of 13 not recommended for new designs 32467 - 0 application note - pcb layout special attention must be paid to component layout when designing high performance serial digital receivers. for background information on high speed circuit and layout design concepts, refer to document no. 521-32-00, ?optimizing circuit and layout design of the gs90005a/15a?. a recommended pcb layout can be found in the gennum application note ?eb9010b deserializer evaluation board? the use of a star grounding technique is required for the loop filter components of the gs9005b/15b. controlled impedance pcb traces should be used for the differential clock and data interconnection between the gs9005b and the gs9000b or gs9000s. these differential traces must not pass over any ground plane discontinuities. a slot antenna is formed when a microstrip trace runs across a break in the ground plane. the series resistors at the parallel data output of the gs9000b or gs9000s are used to slow down the fast rise/fall time of the gs9000b or gs9000s outputs. these resistors should be placed as close as possible to the gs9000b or gs9000s output pins to minimize radiation from these pins. (1) to reduce board space, the two anti-series 6.8 f capacitors (connected across pins 2 and 3 of the gs9010a) may be replaced with a 1.0 f non-polarized capacitor provided that: (a) the 0.68 f capacitor connected to the osc pin (11) of the gs9010a is replaced with a 0.33 f capacitor and (b) the gs9005b /15b loop filter capacitor is 10 nf. (2) remove this potentiometer if p/n function is not required, and ground pin 16 of the gs9010a. (3) the gs9000b will operate to a maximum frequency of 370 mbps. the gs9000s will operate to a maximum of 300 mbps. fig. 16 typical application circuit all resistors in ohms, all capacitors in microfarads, all inductors in henries unless otherwise stated. standard truth table ?/2 p/n standard 0 0 4:2:2 - 270 0 1 4:2:2 - 360 1 0 4?sc - ntsc 1 1 4?sc - pal p/n out in- comp lf ?/2 v cc swf parallel data bit 9 parallel data bit 8 parallel data bit 7 parallel data bit 6 parallel data bit 5 parallel data bit 4 parallel data bit 3 parallel data bit 2 parallel data bit 1 parallel data bit 0 parallel clock out sync correction enable hsync output sync warning flag stdt v cc cd hsync gnd osc dly fvcap 0.1 10 10 + + +5v +5v 100 100 100 100 390 390 390 390 25 24 23 22 21 20 19 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4 3 2 1 28 27 26 12 13 14 15 16 17 18 910 5.6p 10n (1) (1) (1) (2) 0.1 0.1 3.3n 82n 180n 0.68 0.1 0.1 22n dgnd dgnd dvcc dgnd dvcc vcc dgnd gnd dgnd 0.1 serial digital input 1.2k 1.2k 68k 100 100 dvcc dvcc dgnd dgnd 120 50k 0.1 100k gs9010a dd i dd i vcc1 vee1 vee1 ?/2 vee3 sdo sdo sco sco ss1 ss0 cd vee1 vee1 vee1 vee1 vee1 vee2 vcc3 loop rvco0 rvco1 rvco2 vee3 rvco3 vcc2 25 24 23 22 21 20 19 5 6 7 8 9 10 11 4 3 2 1 28 27 26 0.1 100 100 100 3.3k 100 100 100 100 100 100 100 gs9000b or gs9000s pd7 pd6 pd5 pd4 pd3 pd2 pd1 vss swf vss hsync pd9 pd8 vss vdd vdd sce swc pclk pdo vdd star routed 12 13 14 15 16 17 18 vcc vcc vcc vcc vcc vcc vcc vcc swf vcc 6.8 6.8 + + gs9015b sd i sd i sc i sc i ss1 ss0 sst swf (3)
13 of 13 32467 - 0 not recommended for new designs gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that the y are free from patent infringement. ? copyright july 2004 gennum corporation. all rights reserved. printed in canada. document identification: data sheet the product is in production. gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. revision notes: new document. for latest product information, visit www.gennum.com gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax +1 (905) 632-2814 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 gennum japan corporation shinjuku green tower building 27f 6-14-1, nishi shinjuku shinjuku-ku, tokyo 160-0023 japan tel: +81 (03) 3349-5501 fax: +81 (03) 3349-5505 gennum uk limited centaur house, ancells business park, ancells road, fleet, hampshire, uk gu13 8uj tel. +44 (1252) 761 039 fax +44 (1252) 761 114

▲Up To Search▲

Price & Availability of GS9015BCPJ

	To Download GS9015BCPJ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .